I’m officially working on my SystemVerilog. I finished the ALU, PC Register, and the Register File, with tests for all of them using AMD Vivado (I plan on flashing to an Artix 7). They have a cool new dark mode, which is way easier on my eyes. I’ve also done a lot of research, specifically on the DMAC, which I plan to add. It’s basically a really small and specialized mini-core of sorts, and its sole purpose is to read from storate and write to memory, then interrupt, and vice versa (this way, the CPU doesn’t waste millions of cycles for the slow hard drive). I’ve already thought about how I want to make mine, and have started drawing one out.