HDL CPU
- 1 Devlogs
- 1 Total hours
Implementation of a single cycle CPU in Verilog with Von Neumann memory organization
Implementation of a single cycle CPU in Verilog with Von Neumann memory organization
Figured out HackaTime! Wrote the beginnings of my program counter and memory modules. My program can read the contents of a .txt file, which will eventually be divided into instructions and computer memory.
