Luxera Smart Glasses
Hardware- 4 Devlogs
- 32 Total hours
Last log the frame was gray boxes. Now it is built around my own prescription lenses, the front dropped 13.4 mm, every open decision is closed, and some things still look bad.
The front frame went from 57.9 mm tall to 44.46 mm. Derived, not guessed: my traced lens height (37.46 mm, confirmed against a 37 mm caliper reading) plus a 4.6 mm top rim and 2.4 mm bottom. Normal acetate frames run 40 to 45 mm, so the front is finally eyewear and not goggles. Apertures follow my actual lens contour, and the holes punched through the face are gone, replaced by camera and IR windows inside the corner blocks.
Seating real parts in the real frame surfaced four issues. All resolved:
Not pretending the renders are pretty:
Root cause: code CAD is excellent at holes, pockets, walls and clearances, and bad at smooth flowing eyewear surfaces.
I connected Fusion 360 to Claude Code over an MCP bridge. An add-in runs inside Fusion and the agent gets two tools: execute Python with full API access, and screenshot the viewport. That second one matters most, because the tool can finally see its own work and catch a blob before I do. Code stays master for engineering geometry and verification, Fusion becomes master for the exterior surface, and they meet through STEP.
front-old-vs-new.png: the 57.9 mm slab beside the 44.5 mm framefront_frame-front.png: the new front, following my real lens contourassembly-hook-closeup.png: the lollipop, the defect being deletedassembly-iso.png: current assemblyNext: fix the four defects, sculpt in Fusion, print the right temple and wear it.
Big stretch since the last log: the program crossed from designing into spending mode, the frame became real CAD, and we found a vendor that might cut the biggest cost line in half.
Verification is not paperwork, it keeps catching real things:
Claude Code is the engineering copilot: it writes the KiCad files and the CAD as code and runs for hours. I direct, review, catch the design smells, and make the calls. Nothing counts on vibes: every board answers to real ERC and DRC, every frame part to watertight, wall thickness, and collision checks. Longest single run: 2 days 15 hours.
assembly-iso.png: frame CAD v1, full assemblyassembly-split-open.png: temples split open with the real boards seated insidep-core-bottom.png: the prototype brain, bare RK3566 HDI boardp-front-iso.png: the front board that the new architecture retiresMore soon: a printed temple, real quotes, and hopefully a display engine with a price tag.
Since last devlog the project went from “one schematic” to the entire bench board set finished and fab-ready — and one massive architecture correction.
My custom A* autorouter got each board ~90% routed then hit a wall for days — escape congestion on 0.4mm-pitch connectors that greedy routing can’t solve. Fix: a fully headless pipeline —
KiCad Python API → Specctra DSN → Freerouting (real rip-up-and-reroute) → session import →
kicad-cliDRC as the referee
The CSI fanout that blocked me for days fell in 28 seconds. Humbling.
The plan was a Radxa Zero 3W as the in-frame compute. Deep-dive before committing: it’s HDMI-only. No MIPI-DSI, no QSPI — it physically cannot drive the MicroLED display that the entire product exists for. Also it’s a 65×30mm brick that would never fit a glasses temple.
Killed it. Re-read the build guide cover to cover — the real design was always the bare RK3566 SoC soldered directly onto the temple board, with 2× LPDDR4 + eMMC + Rockchip’s RK817 PMIC around it.
So the real in-frame boards are now underway:
kicad-cli DRC re-reports exclusions the GUI accepts — document every waiver or your CI numbers lie.Next: layout + routing of the in-frame boards. The compute board is 6-layer HDI with DDR length-matching — that one gets a professional design review before any fab money. Then fab packs and the full branded bring-up & testing guide. 🔧
Finished the complete KiCad schematic for Luxera’s Core bench board (the “brain” board that the glasses’ electronics get proven on before shrinking into the frame).
What’s in it:
Hard-won lessons today:
Next: footprint assignment, then the actual PCB layout — 4-layer board, 55×45mm.
Every part verified in stock at JLCPCB/LCSC. Repo committed. 🔧