ID: JAX PR-1

I have made a PR which fixes an issue in jax-ml/jax repo.

Pull Request (PR) URL: https://github.com/jax-ml/jax/pull/38617

Issue URL: https://github.com/jax-ml/jax/issues/38615

ID: Hoppscotch CR-1, 2

Reviewed 2 PRs in the Hoppscotch repo.

URLs:

1. https://github.com/hoppscotch/hoppscotch/pull/6381
2. https://github.com/hoppscotch/hoppscotch/pull/6447

ID: Tensor Flow PR-1

Summary

This PR resolves an optimization trajectory divergence bug (detailed in #120986) that occurs when utilizing tf.nn.compute_average_loss inside a distributed multi-worker training loop (MultiWorkerMirroredStrategy) wrapped with XLA compilation (jit_compile=True).

Root Cause Analysis

The optimization trajectory splits between the non-XLA (reference) and XLA-compiled execution arms because of how active strategy contexts are evaluated across the function tracing boundary.

Historically, compute_average_loss relied exclusively on distribute_lib.get_strategy().num_replicas_in_sync to infer the global batch size scaling constant. This utility queries the thread-local strategy_stack maintained by the eager runtime context. However, during the graph tracing initialization phase of tf.function(jit_compile=True), this eager stack handle can become isolated or masked inside the polymorphic function builder thread space. Furthermore, if a trace is evaluated prematurely or during initialization steps, the stack can appear empty to the compilation tracer frame.

When this handle is masked or evaluates to empty, compute_average_loss silently falls back to a default global_batch_size = 1. Under XLA, this value is permanently constant-folded and baked directly into the HLO binary graph. During actual parallel execution inside strategy.run(), the underlying math executes math_ops.reduce_sum(per_example_loss) / 1 instead of dividing by the correct num_replicas_in_sync (e.g., 2). This permanently doubles the gradient magnitude on the XLA arm, causing stateful optimizers like Adam to immediately diverge.

Implementation Details

1. Context Resolution Pipeline: Added a new private utility helper _get_num_replicas_in_sync() inside tensorflow/python/ops/nn_impl_distribute.py. This helper modifies the strategy discovery topology to prioritize checking the lightweight, per-thread active environment handle distribute_lib.get_replica_context(). This context is guaranteed to be populated inside strategy.run() and cleanly survives the Python frame switches involved in XLA function tracing.
2. Defensive Invariants: Added type and range validation assertions to ensure the resolved replica integer count is a strictly positive Python int to catch structural strategy bugs prior to HLO constant generation.
3. Caller Redirection: Refactored compute_average_loss to route dynamic scaling factor discovery through the new _get_num_replicas_in_sync() pipeline.
4. Testing Harness expansion: Appended comprehensive unit and integration regression test suites (TestGetNumReplicasInSync and TestComputeAverageLossXLAContextMasking) directly to tensorflow/python/ops/nn_loss_scaling_utilities_test.py to formally mock context-masking behavior and assert proper scalar output reductions under isolated tracing simulation environments.

Verification Status

• Syntactic and AST structural verification passes cleanly via py_compile checks.
• Code style preserves the 2-space baseline indentation layout standard to the internal package architecture.

ID: PyTorch PR-1

I have force-pushed an updated, compile-safe implementation to address the logical and architectural edge cases across both the CPU and CUDA backends.

Core Changes & Fixes:

• Compile-Time Branching (CPU & CUDA): Added C++17 if constexpr (std::is_integral_v<scalar_t>) branching to decouple the type dispatch loops. This completely isolates the NaN-preservation logic to floating-point types (float, double, Half, BFloat16). As a result, integral type paths completely elide the isnan guards at compile time, eliminating template instantiation errors and preserving the highly optimized native fast paths.
• CUDA Host-to-Device Fix: Inside sign_kernel_cuda, the host-side at::_isnan utility inside the GPU_LAMBDA has been replaced with the device-safe qualified c10::isnan intrinsic. This resolves the NVCC __host__ to __device__ namespace violation completely.
• Validation: The updated files have been verified locally. Both spin lint and lintrunner -a pass with zero code style or formatting errors, and local target compilation succeeds perfectly.

The PR is now fully production-ready and structurally sound.

Improved the K-VL library.

ID: PyTorch PR-2

Another lint error fixed.

ID: PyTorch PR-2

Fixed the lint error in PyTorch PR-2.

ID: PyTorch PR-2

Summary of Upstream Work

Investigated and resolved a silent miscompilation bug in torch.compile where abs() operations on unsigned integer tensors (such as uint8) routed through the C++ codegen produced incorrect downstream graph results (Fixes #187018).

Engineering Execution

• Root Cause Diagnostics: Identified that the TorchInductor CPU codegen emitted std::abs({x}) unconditionally for scalar paths. In C++, std::abs lacks an overload for unsigned types, triggering implicit signed integer promotion that broke critical downstream unsigned wrap-around semantics during negation and reduction.
• Fix: Modified CppOverrides.abs() within torch/_inductor/codegen/cpp.py to handle types explicitly. Unsigned integers now bypass C++ math entirely as an identity operation (x), signed integers utilize a typed ternary bypass to avoid implicit promotion, and floating-point paths preserve the standard std::abs({x}) fallback.
• Validation & Testing: Authored a targeted regression unit test (test_uint8_abs_codegen_issue_187018) within test/inductor/test_torchinductor.py under CpuTests. Verified that eager and compiled outputs now align flawlessly with strict parity.

ID: PyTorch PR-1

This patch resolves a critical numerical divergence inside the PyTorch core library regarding how torch.sign handles NaN (Not a Number) floating-point elements. By replacing relational comparison dependencies with an explicit NaN-interception architecture, this modification ensures strict adherence to modern IEEE 754 floating-point standards and unifies execution parity across both CPU (SIMD Vectorized) and GPU (CUDA Threaded) runtimes.

Engineering Deconstruction

1. The Architectural Flaw (The Root Cause)

Previously, both the CPU and CUDA hardware backend kernels computed the numerical sign of a tensor element using raw relational comparison arithmetic expressions equivalent to:

$$\text{Result} = (0 < a) - (a < 0)$$

According to the IEEE 754 specification, any relational comparison operations evaluated directly against a NaN element must return false. Because of this constraint, when a NaN entered the execution block:

• $0 < \text{NaN} \implies \text{false} \ (0)$
• $\text{NaN} < 0 \implies \text{false} \ (0)$
• $\text{Result} = 0 - 0 = 0$

This configuration silently swallowed the arithmetic NaN state, transforming an undefined input value into a normal, valid 0 tracking tensor, which broke expected downstream behavior in mathematical gradients and loss validation.

2. The Multi-Backend System Fix

To fix this without degrading processing speeds, the implementation handles the problem at the hardware compilation level for both devices:

• Advanced CPU Kernel Path (UnaryOpsKernel.cpp):

• Scalar Fallback: Integrated an immediate type-safe intercept layer using at::_isnan(a). If true, the branch bypasses relational arithmetic entirely and returns the original NaN element.

• SIMD Vectorization: Packaged hardware registers to calculate masks using self_vec.isnan(). It applies a precise bitwise rewrite step via Vectorized<scalar_t>::blendv to preserve original uncorrupted data lanes right before register return.

• Parallel GPU Kernel Path (UnarySignKernels.cu):

• Upgraded the global device execution lambda ([]GPU_LAMBDA) to intercept thread blocks via at::_isnan(a) before the variable drops down into the low-level c10::signum(a) macro block.

Kinetic-AG

A Neuro-Symbolic Program Synthesis Framework for Fluid General Intelligence on ARC-AGI-2.

── Abstract

Current Large Language Models excel at static retrieval and pattern replication, but they fundamentally fail at fluid intelligence—the ability to adapt to novel, unseen problems without explicit training data. The ARC-AGI-2 benchmark exposes this “Overfitting Trap” by forcing models to solve abstract visual-logic grids using fundamental Core Knowledge Priors.

Kinetic-AG is an advanced neuro-symbolic framework designed to bypass the limitations of raw neural pixel-guessing. By transforming a generative model from a predictive writer into an autonomous programmer, Kinetic-AG uses test-time program synthesis and automated code verification to solve multi-step geometric transformations with mathematical certainty.

── The Architecture

Kinetic-AG splits the cognitive load between neural perception and symbolic execution through two core pillars:

1. K-VL (Kinetic Vision-Logic Library)

Instead of forcing the model to write complex NumPy matrix math from scratch—which introduces a high risk of syntax drift and boundary errors—we engineered K-VL, a custom Domain-Specific Language (DSL) embedded in Python.

K-VL maps directly to human Core Knowledge Priors across four specialized modules:

• K_Space: Dynamically manages variable grid layouts, topology, and dimensions.
• K_Objects: Performs connected-component labeling to isolate, categorize, and filter spatial entities by color, coordinate geometry, or size.
• K_Transform: Executes physics-safe translation vectors, clockwise/counter-clockwise rotations, and axial mirroring.
• K_Color: Employs an optimized, graph-based Breadth-First Search (BFS) flood-fill engine for rendering complex painting logic.

2. Test-Time Program Synthesis & Automated Verification

Kinetic-AG does not execute blind predictions on unseen test data. The framework implements a strict runtime execution gatekeeper (verify_engine):

1. Hypothesis Generation: The core reasoning engine analyzes the visual patterns of an active puzzle and outputs a custom Python execution script using K-VL syntax.
2. The Crucible (Sandbox Testing): The framework dynamically compiles the script inside an isolated local sandbox, executing it against all given demonstration pairs (which dynamically scale up to 10 pairs depending on the task specification).
3. Automated Rejection Sampling: If the script fails to match the output matrices of the demonstrations by even a single pixel, it is instantly rejected. The runtime error trace is recycled, and the engine generates a refined hypothesis.
4. Verified Execution: Only when a code block achieves a perfect 100% validation rate across every single example pair does the framework execute the solution on the hidden test grid.

── Engineering Journey & Robustness Testing

Building Kinetic-AG required navigating structural variations introduced in the updated arcprize/ARC-AGI-2 specification, where input spaces, training pair sizes ($\le 10$), and target evaluation counts ($2\text{ to }4$) fluctuate wildly.

To guarantee architectural stability before scaling up computational training loops, we engineered an end-to-end data auditor script. We executed a mass robustness sweep across the entire official dataset, running thousands of extraction passes.

The Result: The K-VL pipeline achieved a perfect, crash-free stability rating across the multi-grid structures of the dataset, logging every spatial metric into a structured compilation framework (kvl_audit_report.json) to serve as our downstream training profile.